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ASIC Design For Signal Processing

By Geoff Knagge

[Last modified 11:12:40 PM on Tuesday, 27 July 2010 2003]
[A note on updates]

Wednesday, 23 January 2019


These project pages are based on the website as part of the submission of my final year uni project, during 2003. The motivation to this project comes from the industrial experience that I completed with the former Bell Labs Australia between December 2001, and February 2002 (the Australian group is now part of Agere Systems, but Bell Labs is the research group of Lucent Technologies). The primary focus of this research group is wireless communications systems, and the development of digital chips to meet the demands of the next generation of high performance wireless technologies. The topic of my work was multiplication circuits, with the challenge to either match, or improve on, the speed of a benchmark multiplier that was already in existence in the Lucent component library.

This target was exceeded, with a design that was 14% faster than the existing multiplier, and in some cases matched the speed of the non-configurable design that was built into the synthesis software. My project involves extending this work, and using it to build a much more involved design.

An ASIC Design

ASIC is an acronym for Application Specific Integrated Circuit. It refers to the technology that many chip designers, including Lucent, use for the physical creation of their chips. This project focuses heavily on the creation of such a design, which will be incorporated as part of one of Bell Lab's future research chips. More information about ASICs, and their FPGA counterparts, can be found on my overview of digital design.

For Signal Processing

A new algorithm has been developed within Bell Labs, that is planned for use in a research chip that is currently under development. The project of this thesis has thus been to implement that algorithm in hardware, by writing a VHDL description of a circuit that can be synthesised into a chip. The particular nature of the algorithm cannot be revealed at the time of writing, but it requires a number of matrix multiplications, using complex numbers. However, it is the implementation aspect that is of particular interest in this project.

Aims of the project

The following specifications describe the challenge that needed to be met

  • Implement the algorithm in a design that uses 8ns clock cycles
  • It needs to use as few clock cycles as possible for the matrix multiplications.
  • It needs to employ optimisations to use as little power as possible
  • It cannot use an excessive amount of space on the chip in which it will be implemented
Since the particular application cannot be discussed, this project has been extended to present a generic set of techniques, which could ultimately be adapted to implement any algorithm primarily based on matrix multiplications.

Scope of the project

This project involved much more than simply implementing an algorithm. In order to create a VHDL model, it was necessary to
  • Refine and further optimise the multiplier circuits which I had previously built
  • Adapt these multipliers to operate on complex numbers. This required researching various architectures, and selecting the most appropriate design.
  • Invesitate, design, and build various architectures for matrix multipliers. One of the requirements is that they were to be able to handle matrices of generic sizes, so that they could be adapted for later projects.
  • Design a data path and architecture for incorporating a matrix multiplier design into the signal processor. One of the requirements was that the single matrix multiplier entity be able to handle the different types of matrix multiplication scenarios that are described on the matrix multiplication page.
  • Generate mechanisms for testing the correctness of the designs
The operation of the algorithm had already been simulated in a MATLAB script, but this used floating point numbers of high precision. This had little use, other than to illustrate the behaviour of an ideal implementation of the algorithm. In practice, it was infeasible to create a floating point implementation in hardware for three important reasons:
  • Impracticality in terms of the physical space which would be required on the chip
  • The amount of time required by the circuit to implement the entire algorithm would be too large
  • The power consumption of such a circuit would be undesirably high
The only alternative approach was to implement a fixed-point model. That is, the implementation would manipulate pieces of data with precision of a fixed number of binary bits, and with a predefined range and number of fraction bits.

Hence, the task was then to take the floating point MATLAB model, and modify it to emulate the behaviour of a fixed-point model. When that was done, it was necessary to examine the effects of adjusting the various parameters, to determine the combination required to balance performance with ease and simplicity of implementation. Finally, the script could then be modified to generate sets of test data for use in verifying the VHDL implementation.

Results of the project

The result has been a signal processor that is a fast as possible with the given design specifications. Furthermore, it contains optimisations to minimise power consumption, and is based on a multiplier circuit for which a patent has been filed. This website, and the associated thesis, presents a set of techniques which could ultimately be extended to implement and matrix multiplication based algorithm.

A note on updates

This website has been submitted as part of the formal assessment process. Therefore, it has needed to remain fairly static from May 31 until whenever the marks are done.

The only change I have made is to upload a demo program, which demonstrates the implementation of the techniques described on this website and in the thesis. It was originally intended to be used at the project open day, but since I was exempted from that, the only way to make it available was to place it here.
(C)opyright 2001-2010, Geoff Knagge.
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