ELEC170 Design Project :

The Voting Machine

Designed and documented by Geoff Knagge

About this Document

This document describes an electronic voting system, including how it works, how it was designed and partial circuit diagrams. It also describes how the circuit may be expanded if required. This document and its implementation (as Multimedia Logic files) are available online at http://members.xoom.com/gogogeoff/uni/elec170/.
Images are screenshots from the Multimedia Logic software.
I can be contacted by email at geoff.knagge@studentmail.newcastle.edu.au with any enquiries.
Numbers printed in ^superscript refer to a component with the matching number in the corresponding diagram.

Project Aims and Requirements

The aim of this project is to use digital logic circuits to implement an electronic voting system, designed for elections where a preference is entered for each candidate. It consists of a custom number of voting points ("units") from where voting takes place, and a server which collects the vote data for later use. Although the design doesn't rely on how many units are linked together, there is a practical limit as will be explained later. The Project has been designed subject to the following constraints, listed by category :

Unit Requirements

Must accept up to 15 candidates
Must be able to adjust the number of candidates that are being voted for, with irrelevant buttons disabled.
Voters select candidates in order of preference
Must be able to go back and change choices before submitting a vote
There should be prompts to tell the user what to do
Users choices should be visible via 7 segment displays

Security Requirements

The following precautions are implemented so that people may only vote once, must enter a valid vote, and to indicate that they actually bother to vote at all :

Units can only be used if enabled by an external switch - in this case the "enable booth" button
The unit must be in the inactive state upon wake-up
Votes cannot be submitted until all preferences are filled
Once a vote is sent, the unit displays are cleared and it reverts to inactive mode
Visual Indicators for when a valid vote is ready to send, and when the voter has finished his voting (to show that the person actually did vote)
Votes cannot be submitted until all preferences are entered
The buttons should be made inactive while data is being sent, to prevent corruption of the vote data.

Network Requirements

Units are linked to a "server unit" which collects data when a vote is submitted. This server writes the data to a file for processing by a computer program at some future date.
Units are linked in a style of ring network to minimise necessary cabling in a real life situation. Data transmission is controlled by a "token passing" style arrangement.
The server should self generate a new token and audible alert in the event that something goes wrong and the token gets lost.

Design Methods

Due to the complexity of the device, it became apparent that the circuit would need to be broken up into smaller sections, each of which preformed its own specialised task. The final modules and how they interconnect is illustrated in the diagram below.

When determining how the unit should be divided up, and also to determine the logic required in each section, the design requirements had to be examined to work out what functionality was required. The conditions required for each functional part were then decided, and from this the necessary logic could be determined. In each of the following descriptions of how each section of the unit works, the basic description was determined before the logic was implemented.

Since all sections could easily be designed in this manner, the result has been that no truth tables or Karnaugh maps were necessary for this project. However, an alternative design for the counter section is included as an appendix, to demonstrate how Karnaugh maps and state transition tables can be used to design such a circuit.

Section 1 : The Keypad Interface

This is the user interface with the voting machine. For each candidate, it contains a selection button¹², a seven segment display¹⁰ to show what preference is currently entered for that candidate, and some logic used to control clocking of other parts of the circuit.

Each candidate button sends out an individual signal to sections 2 and 3, as well as to a set of OR^{13, 14} gates. These OR gates clock the memory writer and counter whenever a candidate button is pressed. The above circuit diagram is shown incomplete, but the implementation of this circuit has each or the first OR gate's¹³ inputs connected to the AND gate of other buttons, similar to what is shown. The four input OR gate¹⁴ is connected to other OR gates which have the same function as the one shown¹³.

A "back" button¹⁵ is used so that the user can adjust their choices by deleting their last entry. Since the counter is incremented after each preference is assigned, it must be decremented before the button assigned to the last entered preference can be cleared. The CntDir signal decrements the counter, the buffers¹⁷ give the circuit time to adjust by delaying the signal 1 cycle per buffer. The Back signal clears the last preference that is entered.

There is also a mechanism to prevent any of the buttons having any effect while the vote data is being sent to the server. During this time, the Button signal is low, and thus none of the connected AND gates^{11, 19} can be activated. Candidate buttons are further restricted by the #Active signals, which go low whenever a button has already been used for this vote, or if the button has been deactivated (when there are more buttons than candidates). The Submit Vote button¹⁸ will only do anything when the allfilled signal is high. This only occurs when all #Active signals are low.

The Reset section is protected in a slightly different way. It is controlled by an RS latch, which is set whenever the Wake-up, or Enable buttons are pressed. If this were a real life implementation, these switches would be located remotely to prevent people submitting votes unless they are supposed to. Until the reset button is activated and pressed, the key circuit will not function because the Button signal will be low.

The circuit is reset whenever the wake-up¹ or reset⁵ buttons are pressed, clearing the keypad^keyrst, counter^CntRst and key locking^Reseta subcircuits. The keypad is also reset when the unit sends vote information to the server, so that the choices are not visible when the next person uses the circuit.

LED indicators are used to show when a vote is ready to be submitted, and when the booth is not enabled (a vote has been completed).

Section 2 : Setting which keys are active

This part of the circuit determines which candidate buttons are active. A button is active if that button has a corresponding candidate for the election, AND^{2, 4} if that button has not already been used during the current vote.

The selection switch⁷ is used to determine how many candidates there are, with the switch value being set one higher than the number of candidates. This produces a binary value used to drive the two demultiplexors^{6, 8}, where the output corresponding to the value of the appropriate candidate is set low. The corresponding button, and all further buttons then become inactive.

The design for this section was fairly intuitive given the requirements of the module. We need a mechanism to determine which buttons are allowed to be active, and this is achieved by the switch and the multiplexors. The first button which can't be active has a low logic level fed to it. However, a button is not allowed to be active if the one before it isn't allowed to be active. Hence we have the cascaded AND gates^1,3. Finally, if a button is allowed to be active, it can only be active if it hasn't already been used^2,4.

Finally, to determine whether the vote is ready for processing, we have to check that all the buttons are inactive. This is achieved by the equivalent of a 16 input NOR gate⁵, which will remain low if any of the buttons are still active

To expand the circuit to cope with up to 127 candidates, we would require a switch with a 7 bit output, and 14 extra 3:8 demultiplexors with additional demultiplexors to determine which of the former are active, or their equivalent. In addition, each candidate requires its own pair of AND gates, along with #Active and NoHit# signals. A 128 input NOR gate would require two more cascades of OR gates than the 16-input version shown here.

Section 3 : Decoding the button pressed into a 4-bit output

Each bit has a compound OR gate, with each input linked to the signals which activate that bit. For example, Vote1b activates S0 only, and Vote3b sets S0 and S1 high. The shown circuit is for a 6 candidate system, with room to implement circuitry for 8 candidates. To modify the circuit for up to 15 candidates, the buffer⁸ needs to be replaced by an OR gate, and the OR inputs^5,6,7 which are tied low need to be linked to additional OR gates, which are in turn driven by the additional signals Vote9b to Vote15b.

If this system was to handle 127 candidates, we would need 3 extra outputs, and 1 more cascade of OR gates since each bit could be activated by any of 64 buttons. In addition, section 5 would need to be adjusted for the extra 1 cycle delay that would be incurred by the extra cascade of OR gates.

Section 4 : The Key Control Centre

This is the section that does most of the processing concerned with the candidate keys, each of which has its own copy of the circuit. The section surrounded by the red box is duplicated 4 times for each key, with each copy connected to a different input on the AND gate.

We require that this module remembers the preference assigned to each key, so we require 4 D-latches. The output of these latches goes to the seven segment displays in section 1. We also need to know whether the button has been used during the current voting session. This is done with an RS latch which is set whenever that button is pressed, and reset upon a keyrst signal OR⁵ a successful Back signal. The D-latches are clocked whenever the appropriate Vote# signal is detected AND NoHit# is high.

The job of the Back signal is to reset the state of the respective key so that it may be used again. However, this can only occur if the value of the next preference to be entered is the same as that stored in the D-latches. This is determined by the XNOR gates and the 4 input AND⁷, which then allows the Back signal to proceed if this condition is met.

The remaining component which requires explanation is the tristate gate. This was used in the simulation due to the problem that there was no way to "turn off" the seven segment displays. They always display a number, or "U" for unknown. The role of the tristate gate here is to force the displays into the Unknown state if the key hasn't been used, or show the appropriate number if it has. If RS latch's Q output is high, the tristate's other input propagates to its output, otherwise the output is "unknown". In a real situation, we would not use the tristate at all, instead controlling the display's power pin with the RS latch.

To expand the voting machine here is fairly easy. All we need is a new copy of the circuit for each button. However, instead of the 4-input AND gate we would need the equivalent of and 7-input AND, and 3 more copies of the outlined section for each button. The 7-input AND would be best achieved by using a 3-input and 4-input AND, and replacing the 2-input AND with a 3-input AND to allow for this addition. If more than 9 buttons are used, additional circuitry would be needed to convert the output to multiple digit displays.

Section 5 : The Memory Module

The memory module stores the values of the buttons in the order that they are pressed, and retrieves these values when the unit needs to send the vote to the server.

The input section is simple : the MemWrt signal comes from section 1 whenever a candidate key is pressed, and the bit values come from section 3. Outputs are sent to section 7.

Where the memory address input comes from needs to be dependant on whether the circuit is in the mode where it is sending data to the server. If this is NOT the case, the address determined by section 6 is used. Otherwise, the address comes from the 4 bit counter, clocked by section 7 as each byte is required.

To expand this module for 127 candidates, we need three additional inputs corresponding to the outputs that need to be added to section 3. The Address and Output sections also need to be expanded for 7 bits, and the counter replaced with a 7 bit version. In addition, as described in section 3, buffers would have to be placed between the MemWrt and each of the A# signals, to compensate for the 1 cycle delay caused by expanding section 3.

Section 6 : The Counter

The counter is used to determine what preference number is entered when a candidate button is pressed, and also for addressing the memory. Depending on which signal is clocked, it will count up or down, wrapping around to 0 if it counts past 15, but staying at 0 if it tries to count lower.

If is built out of four D-type flip flops, with the top diagram showing how the value of the data input is determined. While not necessarily the most efficient logic to achieve the job, it makes the circuit easiest to expand if more data bits are required. An alternative design is described as an appendix. The Data fed into the flip flop is either the result of an adder OR⁶ a subtractor. The XOR⁷ gate and Q_x input are common to both, with the OR6 gate selecting whether the other input is fed adder⁵ or subtractor⁴ logic.

The carry in and borrow in signals come from the bit that is one position less significant than the current one. The Carry for the LSB is tied high, and the Borrow driven by a 4-input NAND with inputs tied to Q-bar of each of the flip flops. That way, when the counter is at 0000, the NAND gate goes low and no subtraction occurs. No such measure is taken for the carry, since it is assumed that the counter will never be clocked past its maximum value.

The only problem with this design is that the counter cannot be clocked more than once in four cycles, otherwise the carry and borrow signals will not have time to filter through the gates. However, this is of little consequence in this application, since the machine takes just as long to do its other tasks.

The right diagram shows the logic used to clock the flip flops. The missing input on the AND³ gate comes from the Data out signal of the above section, and the buffers are used to ensure that all relevant signals reach their destination together, and at the correct cycle. The CntRst signal sets all inputs to 0³, and clocks the flip flops, thus resetting the counter. The output addresses the memory module.

Finally, we need to increment the counter's output by one in order to produce a sensible output on the seven segment displays, since the counter's first value is actually zero. This is achieved by use of adders for bits 0, 1⁵, and 2^8,6 with the redundant gates removed.

Bit 3 is determined by a half adder⁹, with the carry in value coming from a 3 input AND⁷ gate. The inputs of this gate are the Q outputs of the first 3 flip flops, since there will only be a carry if the counter's value is of the form "?111".

The buffers ensure that all of the results are output at exactly the same time, although they are not all necessary for the correct operation of the circuit.

Section 7 : The Network Interface

Voting units are arranged in a variation of a token ring network. Units are linked together by some form of data connection (here we use a TCP/IP linkup), and tokens are passed around in the form of a signal on bit 0. When a unit receives the token, it may transmit any data that it has to the server, otherwise it passes the token on to the next unit. If it receives any other data, this must be passed on to the next unit.

The most important part of this section is knowing when to set the outgoing clock so that only meaningful data is sent. A clock signal is generated when either data is passed on straight from the input OR⁹ when the circuit is sending data to the server.

For data to be passed straight through, the unit must not be in sending mode7 AND8 must receive data that it wants to pass on. The latter condition occurs when a clock signal is received¹⁶ AND¹³ either there is no token¹⁰ in this data OR¹² there is no data to send to the server¹⁴. Using these requirements, the above circuit is obtained, with buffers inserted to ensure that signals arrive at their destinations during the correct cycle.

The interface makes use of three SR latches to keep track of the unit's status. It needs to know when a vote is waiting to be sent¹, when the interface has finished sending a vote², and when it is currently sending data⁷.

The latter latch is used to switch the signal generator on and off. It is set when there is a clock, a token, the vote button has been pressed^Votese from 1, AND¹⁵ vote data hasn't already been sent^{Q-bar from 2}. It is reset when the interface has sent all the data available^Overflow OR⁵ when the circuit is reset^Reseta.

Data transmission is also finished² when all of the data is sent, and this flag is reset along with the rest of the circuit^Reseta. Additionally, when the Vote button has been pressed, all buttons become disabled by the Button signal being forced low¹. After voting is complete, but the vote has not yet been sent, a signal³ is used to illuminate a "wait for vote to be processed" indicator.

The token is only passed on when the interface is NOT¹⁴ ready to send data AND¹⁹ a token signal is detected on the input. The buffers, as in other parts of the circuit, control the speed at which signals travel through the circuit. An additional AND²¹ gate stops a token being sent while the unit is in sending mode.

This AND²¹ gate is not really required, but was originally included when the simulation was tested with toggle switches instead of the network connection. If the Token switch remained high for too many cycles (which in reality, it wouldn't), that signal can sometimes be sent to the output before or after²² the unit transmits its own data. In a real implementation, this AND gate could be safely replaced by a buffer connecting to the other buffers²⁰.

Finally, data is output when it is received on the inputs²³ OR²⁵ when it the interface is sending data from the memory²⁴. In the latter case, buffers⁵ ensure that the data is sent at the same time as the clock⁴, while the SendCl signal tells the memory's counter to increment so that the next byte can be retrieved.

A data bit is relayed onto the next unit if a clock signal accompanied that bit AND¹³ either no token was present OR¹⁰ the unit was not ready to transmit its own data^14,15 (described above).

To expand this section to cope with up to 7 bits of data, we only need to use the spare inputs and outputs with appropriate logic. Each bit has its own OR²⁵ and AND^23,24 gates, along with buffers and D# signals coming from other parts of the circuit.

Section 8 : The Network Server

The server eventually receives all data that is passed around the network by the units, and this data is stored, in this case to a file, for later processing by a more capable computer. It is stored only if it is accompanied by a clock signal AND⁴ NOT³ a token signal Only one data bit pathway is shown here, but for each additional bit we only need to add the corresponding buffers¹ and AND² gates.

The other job of this circuit is to generate token signals. This occurs when 16 bytes of data are received⁹ (data has been sent and so a new token is needed), when a token signal is received on the input¹ (no unit sent any data), OR¹⁰ when the circuit times out after not receiving a token within a reasonable amount of time⁸.

Possible Improvements and Enhancements

While the design as described is fully functional, there are a number of possible enhancements which could be made. These were not included in the design so that a working simulation could be obtained, since any further additions caused the software to fail. (8 megs RAM did not seem to be enough on a '486 system, not even under Windows 3.1)

Each unit could be expanded to allow up to 127 candidates, as described throughout this document
The design assumes that multiple buttons cannot be pressed at once. A safeguard could be imposed by placing additonal restrictions on when the Button signal is allowed to activate the button AND gates in section 1.
This design has assumed that data transmission between units is perfect, so no error checking mechanism is included. In a real implementation, in which units would be linked by sets of wires, error checking may not be needed if the clocks were run slow enough to make the effect of noise negligable.
A real life implementation could have and automated wake-up circuit with a discharged capacitor setting the wake-up signal high. Once power is applied, it would charge up and send the wake-up signal low, allowing normal operation to commence.
A possible addition could be a "how to vote button", so that a voter could simply press one button and all the preferences would be filled out for them, depending on what each candidate specifies. This would be incorporated with each candidate button between the existing AND¹¹ and OR gates¹³ as follows :

A toggle switch²⁵ sets whether the unit is in normal or auto mode. In normal mode, a press of a candidate button will send the three input AND¹¹ high, and the signal will the proceed through the connected AND²³ and OR²⁴ gates, and then through the circuit as normal.

In Auto mode, the NOT gate driving the 2 input AND²³ will be low, so button signals cannot travel this way. Instead, they will pass through to the "auto fill-out" circuit. The job of this circuit would be to reset the circuit, then to feed signals to the 2-input AND²² gates of the appropriate candidates, in the correct order. This would probably be achieved by a automatically clocked counter (with a similar arrangement to the one in the interface section) driving the address lines of a corresponding read only memory, with the memory output controlling decoders, which in turn connect to the appropriate inputs²².

Alternative Design for the counter in section 6

Dir	Q3	Q2	Q1	Q0	J3	K3	J2	K2	J1	K1	J0	K0	Q3'	Q2'	Q1'	Q0' 
0	0	0	0	0	0	D	0	D	0	D	1	D	0	0	0	1 
0	0	0	0	1	0	D	0	D	1	D	D	1	0	0	1	0 
0	0	0	1	0	0	D	0	D	D	0	1	D	0	0	1	1 
0	0	0	1	1	0	D	1	D	D	1	D	1	0	1	0	0 
0	0	1	0	0	0	D	D	0	0	D	1	D	0	1	0	1 
0	0	1	0	1	0	D	D	0	1	D	D	1	0	1	1	0 
0	0	1	1	0	0	D	D	0	D	0	1	D	0	1	1	1 
0	0	1	1	1	1	D	D	1	D	1	D	1	1	0	0	0 
0	1	0	0	0	D	0	0	D	0	D	1	D	1	0	0	1 
0	1	0	0	1	D	0	0	D	1	D	D	1	1	0	1	0 
0	1	0	1	0	D	0	0	D	D	0	1	D	1	0	1	1 
0	1	0	1	1	D	D	1	D	D	1	D	1	1	1	0	0 
0	1	1	0	0	D	0	D	0	0	D	1	D	1	1	0	1 
0	1	1	0	1	D	0	D	0	1	D	D	1	1	1	1	0 
0	1	1	1	0	D	0	D	0	D	0	1	D	1	1	1	1 
0	1	1	1	1	D	D	D	D	D	D	D	D	D	D	D	D 
1	0	0	0	0	0	D	0	D	0	D	0	D	0	0	0	0	 
1	0	0	0	1	0	D	0	D	0	D	D	1	0	0	0	0	 
1	0	0	1	0	0	D	0	D	D	1	1	D	0	0	0	1 
1	0	0	1	1	0	D	0	D	D	0	D	1	0	0	1	0 
1	0	1	0	0	0	D	D	1	1	D	1	D	0	0	1	1 
1	0	1	0	1	0	D	D	0	0	D	D	1	0	1	0	0 
1	0	1	1	0	0	D	D	0	D	1	1	D	0	1	0	1 
1	0	1	1	1	0	D	D	0	D	0	D	1	0	1	1	0 
1	1	0	0	0	D	1	1	D	1	D	1	D	0	1	1	1 
1	1	0	0	1	D	0	0	D	0	D	D	1	1	0	0	0 
1	1	0	1	0	D	0	0	D	D	1	1	D	1	0	0	1 
1	1	0	1	1	D	0	0	D	D	0	D	1	1	0	1	0 
1	1	1	0	0	D	0	D	1	1	D	1	D	1	0	1	1 
1	1	1	0	1	D	0	D	0	0	D	D	1	1	1	0	0 
1	1	1	1	0	D	0	D	0	D	1	1	D	1	1	0	1 
1	1	1	1	1	D	0	D	0	D	0	D	1	1	1	1	0

This was the original design for the counter circuit used in Section 6. The excitation table shown above represents the inputs required for the four JK flip flops for each state transition, where D indicates that the logic level can be either 0 or 1. This design was not used because the logic required to correct the problems implementing JK flip flops in the software would have made this more complicated than the design used. By inspection, we can then obtain the logic required to drive most of the inputs: